Hierarchical channel marking in a memory system
US8782485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2012 |
| Grant date | Jul 15, 2014 |
| Priority date | — |
| Expiry date | Jul 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/109
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.