Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques

US8782570B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Jianmin Li · Beijing, CN
• Jing Chen · Fremont, US
• Guowei ZHAO · Milpitas, US
• Taufik Arifin · Santa Clara, US
• Yuan Huang · Redwood City, US
• Soohong Kim · Pleasanton, US
• Vassilios Gerousis · San Jose, US
• Shuo Zhang · Oettingen, DE
• Dahe Chen · Fujian, CN

Key dates

• Filing date: May 7, 2012
• Grant date: Jul 15, 2014
• Expiry date: May 7, 2032

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3947
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or coloring routing track(s). Some embodiments route the physical design with coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Multiple-patterning conflicts may be detected based on the coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Some embodiments route with search-and-repair strategy(ies) to improve or resolve conflict(s). Some embodiments color objects upon their creation, and the layout is thus multiple-patterning design rule clean as constructed.