Patent · US Active

Test bench hierarchy and connectivity in a debugging environment

US8782581B2 · kind B2 · utility

6Cited by

6References

20Claims

0Family size

Assignee

MENTOR GRAPHICS CORPORATION · US

Inventors

Badruddin Agarwala · Pleasanton, US
Tarak Parikh · San Jose, US
Vivek Bhat · San Jose, US
Neeraj Joshi · Morrisville, US

Key dates

Filing date	Jul 12, 2013
Grant date	Jul 15, 2014
Priority date	—
Expiry date	Jul 12, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/33
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

This application discloses a design verification tool to collect messages generated by a test bench during elaboration of the test bench. The messages can identify connectivity corresponding to library components in the test bench. A debug tool can generate a schematic representation of the test bench having circuit symbols corresponding to at least portions of the library components, which are interconnected with trace lines based, at least in part, on the messages. The debug tool can prompt display of the schematic representation of the test bench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.