Method for manufacturing semiconductor device having element isolation portions
US8785290B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 2013 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Jan 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device, the method comprising, forming an opening in an insulating layer, which is formed on a semiconductor substrate, using a photoresist pattern formed on the insulating layer as a mask, forming a first element isolation portion in the semiconductor substrate by implanting an ion into the semiconductor substrate using the photoresist pattern as a mask, forming a second element isolation portion, in the semiconductor substrate, whose outer edge is outside an outer edge of the opening, by implanting an ion into the semiconductor substrate through the opening, and forming a third element isolation portion, which is inside the outer edge of the second element isolation portion, by embedding an insulating member in the opening and removing the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.