Transient voltage suppressor without leakage current

US8785971B2 · kind B2 · utility

Assignee

• AMAZING MICROELECTRONIC CORP. · TW

Inventors

• Che-Hao Chuang · Dashulong, TW
• Kun-Hsien Lin · Danei, TW
• Ryan Hsin-Chin Jiang · Taipei, TW

Key dates

• Filing date: Nov 23, 2011
• Grant date: Jul 22, 2014
• Expiry date: Aug 17, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D8/422

Abstract

A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.