Semiconductor memory device having a low resistance wiring line and method of manufacturing the same
US8785980B2 · kind B2 · utility
2Cited by
1References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2012 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Aug 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8845
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.