Structure for integrated circuit alignment
US8786054B2 · kind B2 · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2009 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Mar 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method and device for pattern alignment are disclosed. The device can include an exposure field; a die within the exposure field, wherein the die comprises an integrated circuit region, a seal ring region, and a corner stress relief region; and a die alignment mark disposed between the seal ring region and the corner stress relief region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.