Delay locked loop
US8786338B2 · kind B2 · utility
2Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2011 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Apr 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.