Method and apparatus for optimizing driver load in a memory package
US8787060B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2011 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Feb 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.