Inhibiting address transitions in unselected memory banks of solid state memory circuits
US8787086B1 · kind B1 · utility
6Cited by
3References
20Claims
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Key dates
| Filing date | Aug 31, 2009 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to inhibiting address transitions in unselected memory banks of solid state memory circuits. Bank selection and address gating circuitry may be used to provide a set of gated address signals to decode circuitry for each memory bank, such that the gated address signals associated with unselected memory banks are prevented from transitioning and the gated address signals associated with a selected memory bank are based on clocking in the status of address signals provided by memory control circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.