Adjusting access times to memory cells based on characterized word-line delay and gate delay
US8787099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2012 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Feb 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory tracking circuit activates a reset signal that resets a word-line pulse generator to switch the memory from an access state to a recess state. Activation is based on (i) a signal received at the far end of a tracking row after a propagation delay and (ii) a signal applied to a transistor-based gate delay. If the memory is in a fast PVT condition such that the gate delay is of less duration than, or substantially equal to, the propagation delay, then a slow-down circuit delays activation of the reset signal to allow sufficient access margin. The delay in the latter case is less than that in the former case. If the memory is in a slow PVT condition such that the gate delay is longer than the propagation delay, then the slow-down circuit does not delay activation of the reset signal to prevent excess access margin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.