Apparatus and method for memory management and efficient data processing
US8788782B2 · kind B2 · utility
0Cited by
26References
9Claims
0Family size
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Key dates
| Filing date | Aug 13, 2009 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Dec 21, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.