Rescaling
US8788987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2011 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Apr 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/347
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.