Deterministic, parallel execution with overlapping regions
US8789060B1 · kind B1 · utility
5Cited by
16References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jul 22, 2014 |
| Priority date | — |
| Expiry date | Mar 8, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, computer program product and apparatus for utilizing simulated locking prior to starting concurrent execution are disclosed. The results of this simulated locking are used to define a canonical ordering which controls the order of execution and the degree of parallelism that can be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.