Method of fabricating a super junction transistor
US8790971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2014 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Mar 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.