Semiconductor device and manufacturing method of the same
US8791574B2 · kind B2 · utility
12Cited by
0References
4Claims
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Key dates
| Filing date | Sep 13, 2012 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Sep 13, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.