Multi-phase frequency divider having one or more delay latches

US8791729B2 · kind B2 · utility

Assignee

• Cisco Technology, Inc. · US

Inventors

• Joachim Heinz Dieter Woelk · Besigheim, DE
• Erwin Robert Schlag · Leinfelden, DE

Key dates

• Filing date: Jun 11, 2012
• Grant date: Jul 29, 2014
• Expiry date: Jun 11, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/42
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.