Patent · US Active

Non-linear-error correction in fractional-N digital PLL frequency synthesizer

US8791733B2 · kind B2 · utility

7Cited by

6References

19Claims

0Family size

Assignee

Intel Mobile Communications GmbH · DE

Inventors

Stefan Tertinek · Graz, AT
Thomas Mayer · Kolbermoor, DE
Christian Wicpalek · Linz, AT

Key dates

Filing date	Oct 5, 2012
Grant date	Jul 29, 2014
Priority date	—
Expiry date	Oct 5, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/085
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.