Modified dynamic element matching for reduced latency in a pipeline analog to digital converter
US8791844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2012 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.