Providing row redundancy to solve vertical twin bit failures
US8792292B2 · kind B2 · utility
0Cited by
9References
20Claims
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Key dates
| Filing date | Mar 11, 2011 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Feb 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.