Updating programmable logic devices in a multi-node system configured for symmetric multiprocessing
US8793480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2012 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Oct 18, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/572
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.