In-hierarchy circuit analysis and modification
US8793633B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2013 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Aug 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modifying a hierarchical circuit design includes: accessing hierarchical circuit data in the hierarchical circuit design; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether inter-block timing closure is achieved; and in the event that inter-block timing closure is not achieved, performing a set of one or more fixes on the selected portion of the hierarchical circuit data to achieve inter-block timing closure. The selected portion of the hierarchical circuit data includes a selected portion of top-level block data and a selected portion of lower-level block data. Accessing hierarchical circuit data, performing timing analysis, and in the event that inter-block timing closure is not achieved, performing the set of one or more fixes are performed within a top-level design process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.