Display and automatic improvement of timing and area in a network-on-chip
US8793644B2 · kind B2 · utility
44Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Jul 29, 2014 |
| Priority date | — |
| Expiry date | Jun 1, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.