Method and system for delta double sampling
US8796036B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2011 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Apr 27, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T436/11
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.