High speed RF divider
US8797069B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2013 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jun 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors. The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.