Low power oversampling with reduced-architecture delay locked loop
US8797075B2 · kind B2 · utility
1Cited by
8References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Aug 18, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4902
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.