Buffer input impedance compensation in a reference clock signal buffer
US8797110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2012 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Sep 12, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.