Efficient header generation in packetized protocols for flexible system on chip architectures
US8798038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jul 1, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/109
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for generating headers in packetized protocols for a flexible routing network for a Network on a Chip (NoC) architecture includes generating packets based on transmission traffic received from an initiator or a target connected to a routing network that connects disparate initiators and targets. Logic to generate the packets is in an interface located between the initiator or the target and the routing network. A header portion of a packet is variable in length and includes a header payload and header control information. Each of the header portion and the body portion includes one or more standard sized transmission units. The size of the transmission units and width of the header payload are determined by logic included in the interface. The width of the header payload is determined based on orthogonal groups with each of the orthogonal groups being associated with targets sharing an initiator thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.