Method and system for processing image data on a per tile basis in an image sensor pipeline
US8798386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2010 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jun 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for processing image data on a per tile basis in an image sensor pipeline (ISP) are disclosed and may include communicating, to one or more processing modules via control logic circuits integrated in the ISP, corresponding configuration parameters that are associated with each of a plurality of data tiles comprising an image. The ISP may be integrated in a video processing core. The plurality of data tiles may vary in size. A processing complete signal may be communicated to the control logic circuits when the processing of each of the data tiles is complete prior to configuring a subsequent processing module. The processing may comprise one or more of: lens shading correction, statistics, distortion correction, demosaicing, denoising, defective pixel correction, color correction, and resizing. Each of the data tiles may overlap with adjacent data tiles, and at least a portion of them may be processed concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.