Chipset agnostic apparatus and method for serial communication bus port disablement
US8799539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2006 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Dec 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information handling system (IHS) includes a host computer with a downstream facing host computer serial communication bus port and a serial communication bus host controller, wherein the controller is configured to detect a serial communication bus device connected to the downstream facing host computer serial communication bus port, wherein the serial communication bus device has a pull-up resistor. The IHS further includes a circuit disposed between the serial communication bus host controller and the downstream facing host computer serial communication bus port, the circuit configured to disable the downstream facing host computer serial communication bus port and comprising at least one tri-state buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.