Method and apparatus for implementing multi-processor memory coherency
US8799584B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2011 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Nov 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for implementing multi-processor memory coherency are disclosed. The method includes: a Level-2 (L2) cache of a first cluster receives a control signal of the first cluster for reading first data; the L2 cache of the first cluster reads the first data in a Level-1 (L1) cache of a second cluster through an Accelerator Coherency Port (ACP) of the L1 cache of the second cluster if the first data is currently maintained by the second cluster, where the L2 cache of the first cluster is connected to the ACP of the L1 cache of the second cluster; and the L2 cache of the first cluster provides the first data read to the first cluster for processing. The technical solution under the present invention implements memory coherency between clusters in the ARM Cortex-A9 architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.