Computer memory subsystem for enhancing signal quality
US8799606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2007 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Sep 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer memory subsystems are disclosed for enhancing signal quality that include: one or more memory modules; a memory bus; and a memory controller connected to the memory modules through the memory bus, the memory controller including a reception buffer connected to the memory bus, the reception buffer capable of receiving an input signal from one of the memory modules, the memory controller including a reception characteristics table capable of storing reception characteristics for each of the memory modules connected to the memory controller, the memory controller including an equalizer connected to the reception buffer and the reception characteristics table, the equalizer capable of equalizing the received input signal in dependence upon the reception characteristics for the memory module from which the input signal was received, and the memory controller including memory controller logic connected to the equalizer, the memory controller logic capable of processing the equalized input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.