Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates
US8799687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2011 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Nov 11, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important observations (1) the bursts of high interrupt rate are interspersed between the low interrupt rate periods and long periods of high activity levels; and (2) the interrupt rate may, suddenly, fall below an interrupt rate (of 1 milli-second, for example) that is typical of the current operating systems (OS). Instead of determining the C-state based on the stale data stored in the counters, the power control logic may determine an optimal C-state by overriding the C-state determined by the OS or any other power monitoring logic. The power control logic may, dynamically, determine an optimal C-state based on the CPU idle residency times and variable rate wakeup events to match the expected wakeup event rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.