Control of digital voltage and frequency scaling operating points
US8799698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Aug 5, 2014 |
| Priority date | — |
| Expiry date | Jun 7, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock signal for electronic circuitry is generated by generating, based on which one of a plurality of application use cases is presently active, a first signal that indicates a first selected one of a plurality of clock signal operating points. Based on the electronic circuitry's present speed requirement, a second signal is generated that indicates a second selected one of the clock signal operating points. For any given one of the application use cases, the speed requirement need not remain constant for the duration of the application use case. Based on whichever one of the first and second signals is associated with a higher clock frequency operating point, a third signal is generated that indicates which clock signal operating point (and possibly what voltage level) should be active. The third signal controls generation of a clock (and possibly also voltage level).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.