Method of inhibiting wire collapse
US8802561B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Apr 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques disclosed herein prevent wire flaking (collapse). One aspect is an improved way of forming wires over trenches, which may be located in a hookup region of a 3D memory array, and may be used to form electrical connections between conductive lines in the memory array and drivers. The trenches are formed between CMP dummy structures. The trenches are partially filled with a flowable oxide film, which leaves a gap in the trench that is at least as wide as the total pitch of the wires to be formed. A capping layer is formed over the flowable film. After forming a conductive layer over the dielectric layer, the conductive layer is etched to form conductive wires. Some of the capping layer, as well as the CMP dummy structures may be removed. Thus, the conductive wires may be at least temporarily supported by lines of material formed from the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.