Resistive memory element and related control method
US8803121B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Mar 9, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.