Self-aligned double-gate graphene transistor
US8803132B2 · kind B2 · utility
13Cited by
11References
20Claims
0Family size
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Key dates
| Filing date | Aug 20, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Aug 20, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/734
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of fabricating a semiconducting device is disclosed. A graphene sheet is formed on a substrate. At least one slot is formed in the graphene sheet, wherein the at least one slot has a width that allows an etchant to pass through the graphene sheet. An etchant is applied to the substrate through the at least one slot formed in the graphene sheet to etch the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.