Power-on-reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage
US8803580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2011 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Oct 17, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a Power-On-Reset (POR) circuit with zero steady-state current consumption and stable pull-up voltage. The POR circuit achieves zero steady-state current consumption during steady operation after the POR process by cutting off a power supply to a band-gap comparator circuit and a current comparator circuit after the POR process. The present invention has high reliability and stable pull-up voltage, is less susceptible to the impact of power-on rate of power supply, temperature, and process variation, has very low steady-state power consumption, and can be integrated in a SOC chip in low-power consumption applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.