System and method for improving speed and power in a switched-capacitor amplifier
US8803721B1 · kind B1 · utility
4Cited by
5References
18Claims
0Family size
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Key dates
| Filing date | Mar 13, 2013 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Mar 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.