Protection circuit for memory control chip
US8804293B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Jan 4, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A protection circuit for a memory control chip of a computer includes a controller, a switch circuit, a memory control chip, and a delay circuit. The controller outputs a high level control signal when the computer is in a first state, and outputs a low level control signal when the computer is in a second state. The switch circuit connects or disconnects the connection between a power pin of the memory control chip and a power terminal, according to the control signal. The delay circuit imposes a predetermined time delay for receiving a high level control signal, and outputs an enable signal to an enable pin of the memory control chip to make the memory control chip operate again, after a predetermined delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.