NVRAM data organization using self-describing entities for predictable recovery after power-loss
US8806115B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Jan 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a parallel (e.g., tiered) logging technique is provided to deliver low latency acknowledgements of input/output (I/O) requests, such as write requests, while avoiding loss of data. Write data may be stored (copied) as a log in a portion of a dynamic random access memory and a non-volatile random access memory (NVRAM). The NVRAM may be configured as, e.g., a persistent write-back cache of the node, while parameters of the request may be stored in another portion of the NVRAM configured as the log (NVLog). The write data may be organized into separate variable length blocks or extents and “written back” out-of-order from the write-back cache to storage devices, such as SSDs, e.g., organized into a data container (intended destination of the write request). The write data may be preserved in the NVlog until each extent is safely stored on SSD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.