Memory access device outputting transfer request
US8806130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2010 |
| Grant date | Aug 12, 2014 |
| Priority date | — |
| Expiry date | Oct 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access device includes a second memory coupled between a processor and a first memory; a memory controller configured to transfer a data from the first memory to the second memory based on a transfer request; a read controller configured to read the data from the second memory, output the data to the processor, and control a read pointer indicating an address reading the data from the second memory; and a write controller configured to output the transfer request to the memory controller, wherein the write controller computes an available capacity of the second memory based on the read pointer, a size of the second memory and a cumulative addition value obtained by adding cumulatively a size of the data which is requested from the processor, and outputs the transfer request based on the available capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.