Patent · US Active

Method and circuit to implement a static low power retention state

US8806416B1 · kind B1 · utility

1Cited by
2References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 28, 2013
Grant dateAug 12, 2014
Priority date—
Expiry dateFeb 28, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318575
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An apparatus to pre-condition an operating integrated circuit (IC) device in a static low power retention state. The apparatus includes a pseudo random number generator that generates a pseudo random number value to pre-condition the static low power retention state of the operating IC device. The apparatus also includes a controller that drives the pseudo random number value into a test scan chain linking logic elements of the operating IC device responsive to the operating IC device entering a sleep mode. Driving the pseudo random number value into the test scan chain by the controller places the operating IC device into the static low power retention state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.