Method for wafer level packaging of electronic devices
US8809116B2 · kind B2 · utility
7Cited by
75References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Dec 6, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.