CMOS transistor linearization method
US8810283B2 · kind B2 · utility
3Cited by
18References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for sampling an analog input signal may include a transistor disposed on a substrate and a sampling capacitor coupled to one of the source and the drain of the transistor. The transistor may be disposed on a substrate that is coupled to ground. A source and a drain of the transistor may be disposed in a back gate of the transistor. The analog input may be supplied to one of the source and the drain of the transistor, and the back gate may receive a back gate voltage having a value that is lower than ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.