Digital power on reset
US8810289B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jun 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatuses, circuits, methods, and other embodiments associated with digital power on reset are described. In one embodiment, an apparatus includes a digital electronic component configured to produce a clock signal. A first counter is configured to output a first count signal based on the clock signal and a second counter is configured to output a second count signal based on the clock signal. A power on reset logic is configured to provide a power on reset signal based on the first count signal and the second count signal, where the power on reset logic is configured to disable the digital electronic component after providing the power on reset signal to prevent the digital electronic component from drawing power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.