Integrated circuit devices and methods
US8811068B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jan 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.