Flash memory system and word line interleaving method thereof
US8811080B2 · kind B2 · utility
7Cited by
2References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2011 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jul 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a flash memory system and a word line interleaving method thereof. The flash memory system includes a memory cell array, and a word line interleaving logic. The memory cell array is connected to a plurality of word lines. The word line (WL) interleaving logic performs an interleaving operation on WL data corresponding to at least two different wordlines and programming data, including the interleaved data, to the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.