Semiconductor memory and system
US8811104B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2012 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Aug 24, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a real memory cell; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a replica circuit including a plurality of replica units connected in series, each of replica units including a plurality of dummy memory cells connected in parallel, wherein one of dummy memory cells of one of replica units is accessed in response to data which is read from one of dummy memory cells of one of replica units of a prior stage; and an operation control circuit configured to activate a dummy access signal to access one of dummy memory cells of one of replica units of a first stage in response to a read command, and to activate the sense amplifier enable signal in response to data read from one of replica units of a last stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.