Memory controller with external refresh mechanism
US8812797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2010 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | Jun 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1668
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same. The effect is that the arbitration between the different requests is rendered less complex. In embodiments of the memory controller there is also an average latency reduction for the high-priority requests. The invent…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.